1. Technical Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly to three-dimensional memory system-on-a-chip (3DM-SoC).
2. Related Arts
The latest advancement of integrated circuits enables the placement of more and more functions on a single chip, thus resulting in wide adoption of system-on-a-chip (SoC). As illustrated in FIG. 1A, an SoC chip 0SOC typically comprises at least one embedded memory (eM) block 0EM and at least one embedded processor (eP) block 0EP. The eM block 0EM provides data storage functions while the eP block 0EP processes the internal and/or external data. The eM block 0EM comprises RAM and/or ROM; the eP block 0EP could comprise logic and/or analog functional blocks.
Because the basic building blocks of prior-art embedded memory and embedded processor are both substrate-based transistors, the eM and eP blocks can be easily integrated on a same substrate. However, it should be noted that the eM block 0EM requires much fewer number of interconnect levels than the eP block 0EP. For example; in the SoC chip illustrated in FIG. 1B, the eP block 0EP uses four levels of interconnect 1EP-IL1, IL2, IL3 IL4, while the eM block 0EM only uses two levels of interconnect 1EM-IL1, IL2. For damascene-based process, within the eM region, the interconnect space 1DY are filled with dummy metals (such as 30d, 40d) and therefore, wasted.
On a state-of-the-art SoC, more than ˜50% of the chip area can be embedded memory. Moreover, the number of the interconnect levels 1EM in the eM region 0EM and the number of the interconnect levels 1EP in the eP region 0EP are quite different (˜3 vs.>˜8). Accordingly, a large interconnect space 1DY is wasted (>˜5 interconnect levels in >˜50% of chip area). To fully utilize this wasted interconnect space 1DY, the present invention provides a three-dimensional memory (3D-M) system-on-a-chip (3DM-SoC). It takes advantage of the fact that 3D-M can be stacked on top of the substrate circuit and does not occupy substrate real estate. Instead of dummy metals, the present invention uses 3D-M to fill in the interconnect space IDY. This 3D-M provides a large storage capacity and is an ideal supplement to the substrate-based embedded memory. As a result, the 3DM-SoC will become more powerful.